1. Field of the Invention
The present invention relates to an improvement of the structure of a solid-state (semiconductor) image sensor.
2. Description of the Prior Art
Conventionally, semiconductor image sensors (referred to hereinafter as SIS) were limited to a MOS type and a CCD type. FIG. 1 shows an equivalent circuit and a reading transistor circuit connected thereto for a fundamental cell (referred to hereinafter simply as a cell) constituting a picture element of a MOS type SIS currently placed on the market. Referring to FIG. 1, a cell is structured by a photodiode PD and a MOS switching transistor TR.sub.S. A charge generated by transducing at the time of application of light to the photodiode PD is stored in a connection capacitance C.sub.V when the transistor TR.sub.S is turned on and then the charge moves to a capacitance C.sub.H when the reading MOS transistor TR.sub.O is turned on, so that the voltage therein becomes a video output. In this case, since the capacitance C.sub.V is as small as 1/100 of the capacitance C.sub.H or less, the signal current becomes a minor current superimposed on the clock noise, as shown in FIG. 2. Accordingly, the dynamic range of the video output is considerably limited and therefore it is necessary to make the photoelectric transducing current sufficiently large by making the light receiving area of the photodiode PD large, thereby to enhance the SIS sensitivity.
FIG. 3 is a sectional view partially showing a cell of a MOS type SIS and the adjacent cells on both sides thereof. In FIG. 3, a p type well 2 serving also as an anode of a photodiode PD is formed on an n.sup.- type substrate 1. An n.sup.+ layer 3 is formed selectively on the surface of the p type well 2 and serves as a cathode of the photodiode PD and also as a source of the MOS switching transistor TR.sub.S. An n.sup.+ layer 4 is formed in P type well 2 so as to provide a channel forming region between this layer 4 and the n.sup.+ layer 3. This layer 4 becomes a drain of the MOS switching transistor TR.sub.S. An oxide film 5 is formed over the p type well 2 including the n.sup.+ layers 3 and 4. A gate electrode 6 made of polycrystal silicon is formed on the portion of the gate oxide film 5 which is over the channel forming region of the MOS switching transistor TR.sub.S. An inter-layer insulating film 7 is formed over the oxide film 5 and the gate electrode 6. In addition, a drain electrode 8 is fixed to the n.sup.+ type layer 4 through an opening formed in the oxide film 5 and the inter-layer insulating film 7. The gate electrode 6 is connected to an interlaced circuit (not shown) and the drain electrode 8 is connected to the reading MOS transistor TR.sub.O. A transistor TR.sub.P (shown by the dotted lines in FIG. 1) formed by the n.sup.+ layer 3, the p type well 2 and the n.sup.- type substrate 1 in the photodiode PD serves to absorb the excess current due to the excessively saturated light.
In order to make the above described MOS type SIS have a high sensitivity, an increase of the area of the n.sup.+ diffusion layer 3 serving as a cathode for the photodiode PD as described above may be considered. However, since the area of application of light to the SIS is determined by an optical system such as a lens etc., the call area is necessarily limited in case where the number of picture elements (i.e. the number of cells) is fixed to a certain value and therefore it is impossible to enlarge the area for cathode arbitrarily. Then, another approach may be considered in which the sensitivity is to be improved by amplifying the photoelectrically transduced signal provided from the SIS. However, in this case, the clock noise of the reading clock and the fixed pattern noise are also amplified and as a result the sensitivity cannot be improved.